From pixels to pipelines.
Real-time rendering, software rasterisation and GPU compute. I work across the CPU–GPU boundary, with attention to frame time, memory traffic and synchronisation.
Explore rendering projectsC++ programmer · Graphics & systems
Graphics, compute &
systems performance.
I'm Jonathan Liu. I build rendering engines, GPU kernels and concurrent C++ infrastructure. My work centres on data locality, explicit synchronisation, resource lifetime and measuring the critical path.
Interested in graphics, GPU computing and low-latency C++ roles, including trading infrastructure.
01
Graphics & compute. Systems foundations.
From events to execution.
I build and measure concurrent queues, cache-aware CPU kernels and asynchronous network services. Trading infrastructure is a career interest; these projects demonstrate the underlying systems work, not a production trading platform.
Explore systems projectsGPU & Graphics
Vulkan 1.3, SPIR-V, Compute Shaders, OpenGL, CUDA Kernel Optimisation, Real-time & Offline Rendering
Languages
C++17 (primary), C, Python, GLSL, Slang, CUDA C/C++, ARM Assembly
Concurrency & Memory
SIMDe / SSE / AVX2, oneTBB, OpenMP, std::atomic, CAS, Reference Counting, Warp Intrinsics, Boost.Asio
Profiling & Systems
Nsight Systems/Compute/Graphics, RenderDoc, perf, ASan / TSan / UBSan, GDB/LLDB, Linux, Docker, CMake
02
Engineering in practice
Real-Time Rendering
Vulkan-Platform
A C++17 Vulkan 1.3 renderer with separate graphics, compute and transfer execution paths. I rebuilt blocking resource uploads around explicit residency, asynchronous transfer submission and deferred reclamation, using Nsight Graphics to inspect the critical path.
Vulkan 1.3
C++17
GLSL / Slang
Compute Shaders
SPIR-V
- Reduced worst-case frame time from 424 to 4.66 ms (~91×) against the same-scene blocking-upload baseline.
- Historical steady-state run: 268 FPS at ~700K triangles and 1.1–1.2K draw calls; CPU queue-submission calls took 0.02–0.1 ms.
- GPU-resident particle simulation: 16,384 particles, 64 × 256-thread workgroups, ping-pong buffers and explicit compute-to-graphics dependencies.
- Timeline semaphores, per-frame contexts and completion-gated resource destruction; inspected with RenderDoc and Vulkan validation layers.
VULKAN / FRAME TIME
4.66ms
Worst-case frame time after upload-path redesign
Before424 ms
After4.66 ms
Historical RTX 3080 Ti Laptop GPU · Windows / MSVC Release · validation disabled for timing. Same-scene worst-case comparison, not a 91× steady-state FPS claim.
CPU Rendering · Portable SIMD · Correctness
Software-Rasterizer
A C++17 CPU renderer with 32 × 32 triangle-to-tile binning, scalar and portable SIMDe raster paths, and a BVH-based Monte Carlo path tracer. Tile ownership keeps framebuffer writes local; SIMD batches depth interpolation and perspective-correct weights while coverage and shading retain shared logic.
C++17SIMDe / AVX2
32 × 32 TilesBVH
Path Tracing
- Same-machine scalar/SIMDe comparison: median draw time 10.866 → 7.790 ms at 1024 × 1024, a 28.3% reduction (1.395× ratio).
- SIMDe p95 / p99: 8.487 / 9.406 ms over 3,000 frames; 1080p p50 / p99: 9.069 / 9.886 ms over 1,000 frames.
- Identical coverage and zero observed maximum depth/color difference between paths in the recorded benchmark runs.
- 21 regression cases cover geometry, visibility, interpolation, scalar/SIMDe agreement, sampling and light transport.
- Offline path tracing includes next-event estimation, cosine-weighted sampling, Russian roulette, and mirror/dielectric scattering.
Workload & timing scope
Recorded 9 October 2026: Apple M5 Pro, macOS arm64, AppleClang 21, Release. TBB was disabled; task scheduling was serial and SIMD used SIMDe on ARM, not native x86 AVX2.
Static Spot mesh, 5,856 input triangles, Phong shading, one point light, no sampled texture. 100 warm-up frames per path per run; 1024² percentiles pooled from three runs. Covered pixels: 13.9% at 1024², so this is not a full-screen overdraw test.
The timer surrounds draw(): clear, preparation, binning,
depth, interpolation, shading and in-draw allocations are included.
Loading, display, image encoding and file output are excluded.
This is draw latency, not full-application FPS; older Intel measurements are not the baseline.
CPU / MEDIAN DRAW LATENCY
7.790ms
SIMDe path · 1024 × 1024 · Apple M5 Pro
28.3%less time vs scalar
9.406 msp99 draw latency
3,000measured frames / path
5,856input triangles
Release · serial scheduling · portable ARM SIMD. Coverage tests and fragment shading are not claimed to be fully vectorised.
CPU / GPU Performance · Concurrent C++
CoreForge
My C++17 performance-engineering library, formerly libHPC. It brings together measured CPU memory-access experiments, a CUDA radix-sort pipeline, sparse storage and concurrent-container prototypes. I pair profiling with numerical checks and lifetime debugging; microbenchmark results are scoped to their workloads.
C++17 / CUDASIMD / OpenMP
Google Benchmarkstd::atomic
ASan / TSan / UBSan
- Reordered strided FP32 matrix accesses into 32-column OpenMP blocks: 97.93 → 11.58 ms (8.46×) for 1024 × 1024 matrices.
- 8192² kernels: 64 × 64 transpose tiling achieved 3.23×; horizontal 17-tap blur with tiling/prefetch achieved 4.55×.
- Four-pass, 256-bin CUDA radix sort: 500M uint32 keys in 360 ms aggregate kernel time (~1.39B keys/s), using warp primitives and a custom hierarchical scan.
- 100M-item queue runs: bounded-ring 4P4C median throughput of 4.80M handoffs/s, 2.69× this project's allocating linked queue.
- Combined TSan, ASan/LLDB and happens-before analysis to repair lost-item and reclamation failures, including consumed-state ambiguity, wrong-node release and empty-pop reference rollback.
CPU results & validation
| Workload | Baseline → optimised | Ratio |
|---|---|---|
| 1024² FP32 matrix | 97.93 → 11.58 ms | 8.46× |
| 8192² transpose | 63.28 → 19.58 ms | 3.23× |
| Horizontal 17-tap blur | 15.72 → 3.46 ms | 4.55× |
| Xyx vertical-blur family | 25.74 → 15.91 ms | 1.62× |
| 1024² / 16²-kernel convolution | 111.08 → 42.55 ms | 2.61× |
| 1 GiB loop fusion | 16.40 → 8.04 ms | 2.04× |
| 512 MiB container lifecycle | 21.33 → 2.41 ms | 8.86× |
Recorded 7 October 2026: ten repetitions with random interleaving, 15 OpenMP threads, no affinity pinning. Convolution is single-threaded and combines 16 × 16 output tiles with four independent reduction chains.
Xyx combines SIMD, prefetching and interleaved accumulators; its 1.62× gain is relative to its own x-tiled baseline. A y-major tiled alternative was faster at 12.34 ms. Container lifecycle includes construction, zero-initialisation and destruction; it is not a random-access throughput measurement.
19 matrix, blur, transpose and convolution variants passed numerical checks on the benchmark inputs. These checks and sanitizer runs provide evidence for the exercised cases, not a proof that every input or interleaving is correct.
Queue throughput, p99 & measurement scope
Apple M5 Pro, Release, unpinned. Throughput uses ten 100M-item runs. Ring medians: 14.4M / 10.9M / 4.80M handoffs/s for 1P1C / 2P2C / 4P4C; these are comparisons with this project's allocating reference-counted queue, not a claim to outperform established queue libraries.
Separate 4P4C latency test at an aggregate 1M handoffs/s offered load: ring / linked p99 = 667 ns / 3.63 µs; p99.9 = 64.83 / 439.50 µs. 100M handoffs, 999K samples. The open-loop interval starts at the planned push time and ends at consumer completion, so scheduling lateness and backpressure are included; it is not the execution time of one queue method.
Separate SPSC handoff p99: 209 / 709 ns (ring / linked). Count, sum, XOR and sample count were checked alongside timing. Debug regressions also use unique-value checks. Recorded tests and an 8-consumer, 8.59B-pop-attempt Release soak completed without recurrence of the previously observed failures; this is not a blanket ABA/race-freedom guarantee.
Queue benchmark source
CPU / FP32 MATRIX MULTIPLICATION
CUDA / HISTORICAL KERNEL-ONLY RESULT
8.46×
97.93 → 11.58 ms · 1024 × 1024 matrices
32 columnsinner-loop blocks
15 threadsOpenMP configuration
ProfileReorderValidate
Apple M5 Pro · macOS Release · 10-run median. Compared with this project's strided baseline, not a vendor BLAS implementation.
CUDA / HISTORICAL KERNEL-ONLY RESULT
1.39B keys/s
500M uint32 keys · 360 ms aggregate kernel time · RTX 3080 Ti Laptop GPU. Not end-to-end transfer/allocation time; not remeasured on the Mac.
Network I/O · Tail Latency
DIMS — Distributed C++ Messaging
A microservice messaging platform with Boost.Asio TCP long-connections, gRPC inter-service communication, custom TLV binary protocol with compile-time safety constraints, with a separately benchmarked TCP connection layer.
Boost.Asio
gRPC
C++17
Redis
Docker
- Isolated TCP layer: 50,000 concurrent loopback connections, 42.8K request-response exchanges/s.
- Recorded p50 / p99 round-trip latency of 0.93 / 5.44 ms; no failed exchanges in the 17.9M-exchange, 50K-connection run.
- Custom SFINAE-constrained TLV serialization across Qt + Boost stacks
- ASan + GDB regression harness for concurrency stress testing
NETWORK I/O / TAIL LATENCY
5.44ms
p99 round-trip time · loopback test
50Kloopback connections
42.8Krequest-response exchanges / s
Historical isolated TCP-layer run: 17.9M request-response exchanges. Not full-service throughput, one-way message rate or production-network latency.
Bare-Metal Systems
ARMv8-A Kernel
Bare-metal bring-up on Cortex-A72 (Raspberry Pi 4B): assembly boot, MMU configuration, interrupt subsystem, and cooperative scheduling — debugged through JTAG, GDB, and UART tracing.
ARMv8-A
C/C++
ARM Assembly
GDB/OpenOCD
- EL1→EL0 exception level transition with full context save/restore
- TTBR-based multi-level page tables for kernel, MMIO, and user-space
- Timer/UART interrupt handling, MMIO setup and SVC trap handling
- Cooperative context switching validated via single-step JTAG debugging
ARMv8-A / EXECUTION LEVELS
EL1EL0
Kernel → user-space transition
MMUIRQContext
Cortex-A72 · Raspberry Pi 4B
Let's talk
Seeking graphics, GPU-compute and C++ performance/systems roles, including low-latency trading infrastructure. Open to opportunities in Shanghai and across the APAC region.