From pixels to pipelines.
Real-time rendering, software rasterisation and GPU compute. I work across the CPU–GPU boundary, optimising frame time, memory traffic and synchronisation.
Explore rendering projects
C++ programmer · Graphics & systems
Graphics, compute &
systems performance.
I'm Jonathan Liu. I build rendering engines, GPU kernels and concurrent C++ infrastructure. My work centres on data locality, explicit synchronisation, resource lifetime and measuring the critical path.
Interested in graphics, GPU computing and low-latency C++ roles , including trading infrastructure.
01
Graphics & compute. Systems foundations.
From events to execution.
Concurrent queues, cache-aware CPU kernels and asynchronous network services. My work focuses on throughput, tail latency, memory efficiency and correctness in performance-critical C++ systems.
Explore systems projectsGPU & Graphics
Vulkan 1.3, SPIR-V, Compute Shaders, OpenGL, CUDA Kernel Optimisation, Real-time & Offline Rendering
Languages
C++17 (primary), C, Python, GLSL, Slang, CUDA C/C++, ARM Assembly
Concurrency & Memory
SIMDe / SSE / AVX2, oneTBB, OpenMP, std::atomic, CAS, Reference Counting, Warp Intrinsics, Boost.Asio
Profiling & Systems
Nsight Systems/Compute/Graphics, RenderDoc, perf, ASan / TSan / UBSan, GDB/LLDB, Linux, Docker, CMake
02
Engineering in practice
Real-Time Rendering
Vulkan-Platform
A C++17 Vulkan 1.3 renderer with separate graphics, compute and transfer execution paths. I redesigned blocking resource uploads with explicit residency, asynchronous transfer submission and deferred reclamation, using Nsight Graphics to profile the critical path.
Vulkan 1.3
C++17
GLSL / Slang
Compute Shaders
SPIR-V
- Reduced worst-case frame time from 424 to 4.66 ms (~91×) through asynchronous resource uploads and deferred reclamation.
- Steady-state run: 268 FPS at ~700K triangles and 1.1–1.2K draw calls; CPU queue-submission calls measured 0.02–0.1 ms.
- GPU-resident particle simulation: 16,384 particles, 64 × 256-thread workgroups, ping-pong buffers and explicit compute-to-graphics dependencies.
- Timeline semaphores, per-frame contexts and completion-gated resource destruction; verified with RenderDoc and Vulkan validation layers.
VULKAN / FRAME TIME
4.66ms
Worst-case frame time after upload-path redesign
Before
424 ms
After
4.66 ms
RTX 3080 Ti Laptop GPU · Windows / MSVC Release · validation disabled during timing · historical same-scene worst-case frame-time comparison.
CPU Rendering · Portable SIMD · Correctness
Software-Rasterizer
A C++17 CPU renderer with 32 × 32 triangle-to-tile binning, scalar and portable SIMDe raster paths, and a BVH-based Monte Carlo path tracer. Tile ownership keeps framebuffer writes local. SIMD accelerates depth interpolation and perspective-correct weights through shared coverage and shading logic.
C++17
SIMDe / AVX2
32 × 32 Tiles
BVH
Path Tracing
- Same-machine scalar/SIMDe comparison: median draw time 10.866 → 7.790 ms at 1024 × 1024, a 28.3% reduction (1.395× ratio).
- SIMDe p95 / p99: 8.487 / 9.406 ms over 3,000 frames; 1080p p50 / p99: 9.069 / 9.886 ms over 1,000 frames.
- Identical coverage, depth and colour outputs between scalar and SIMD paths in recorded benchmark runs.
- 21 regression cases covering geometry, visibility, interpolation, scalar/SIMDe agreement, sampling and light transport.
- Offline path tracing with next-event estimation, cosine-weighted sampling, Russian roulette, and mirror/dielectric scattering.
Workload & timing scope
Recorded 9 October 2026 · Apple M5 Pro · macOS arm64 · AppleClang 21 · Release. Serial task scheduling with TBB disabled; portable SIMDe execution on ARM.
Static Spot mesh · 5,856 input triangles · Phong shading · one point light · 100 warm-up frames per path per run. The 1024² percentiles combine three runs. Pixel coverage: 13.9% at 1024².
Timing scope:
draw(), including clear,
preparation, binning, depth, interpolation,
shading and in-draw allocations.
Loading, display, image encoding and file
output occur outside the timed region.
Metric: draw latency.
CPU / MEDIAN DRAW LATENCY
7.790ms
SIMDe path · 1024 × 1024 · Apple M5 Pro
28.3%
less time vs scalar
9.406 ms
p99 draw latency
3,000
measured frames / path
5,856
input triangles
Release · serial scheduling · portable ARM SIMD · vectorised depth and interpolation · shared coverage and fragment shading.
CPU / GPU Performance · Concurrent C++
CoreForge
My C++17 performance-engineering library, formerly libHPC. CoreForge combines CPU memory-access optimisation, a CUDA radix-sort pipeline, sparse storage and concurrent-container implementations. Development integrates profiling, numerical validation and concurrency debugging across defined workloads.
C++17 / CUDA
SIMD / OpenMP
Google Benchmark
std::atomic
ASan / TSan / UBSan
- Reordered strided FP32 matrix accesses into 32-column OpenMP blocks: 97.93 → 11.58 ms (8.46×) for 1024 × 1024 matrices.
- 8192² kernels: 64 × 64 transpose tiling achieved 3.23×; horizontal 17-tap blur with tiling and prefetching achieved 4.55×.
- Four-pass, 256-bin CUDA radix sort: 500M uint32 keys in 360 ms aggregate kernel time (~1.39B keys/s), using warp primitives and a custom hierarchical scan.
- 100M-item queue runs: bounded-ring 4P4C median throughput of 4.80M handoffs/s, 2.69× the allocating linked-queue baseline.
- Combined TSan, ASan/LLDB and happens-before analysis to resolve lost-item and memory reclamation failures, including consumed-state ambiguity, wrong-node release and empty-pop reference rollback.
CPU results & validation
| Workload | Baseline → optimised | Ratio |
|---|---|---|
| 1024² FP32 matrix | 97.93 → 11.58 ms | 8.46× |
| 8192² transpose | 63.28 → 19.58 ms | 3.23× |
| Horizontal 17-tap blur | 15.72 → 3.46 ms | 4.55× |
| Xyx vertical-blur family | 25.74 → 15.91 ms | 1.62× |
| 1024² / 16²-kernel convolution | 111.08 → 42.55 ms | 2.61× |
| 1 GiB loop fusion | 16.40 → 8.04 ms | 2.04× |
| 512 MiB container lifecycle | 21.33 → 2.41 ms | 8.86× |
Recorded 7 October 2026 · ten repetitions with random interleaving · 15 OpenMP threads · unpinned execution. The single-threaded convolution uses 16 × 16 output tiles and four independent reduction chains.
Xyx combines SIMD, prefetching and interleaved accumulators, achieving 1.62× against the x-tiled baseline. A y-major tiled implementation measured 12.34 ms. Container lifecycle measures construction, zero-initialisation and destruction.
Numerical validation passed across 19 matrix, blur, transpose and convolution variants on the benchmark inputs. Sanitizer testing accompanies the concurrent-container regression suite.
Queue throughput, p99 & measurement scope
Apple M5 Pro · Release · unpinned execution. Throughput measured across ten 100M-item runs. Bounded-ring medians: 14.4M / 10.9M / 4.80M handoffs/s for 1P1C / 2P2C / 4P4C. Reference baseline: CoreForge's allocating reference-counted linked queue.
Separate 4P4C latency test at 1M aggregate handoffs/s offered load: ring / linked p99 = 667 ns / 3.63 µs; p99.9 = 64.83 / 439.50 µs. 100M handoffs, 999K samples.
Open-loop latency is measured from scheduled push time to consumer completion, including scheduling delay and backpressure. The benchmark captures end-to-end queue handoff latency.
SPSC handoff p99: 209 / 709 ns (ring / linked). Validation includes count, sum, XOR, sample count and unique-value regression checks. An eight-consumer Release stress run completed 8.59B pop attempts with zero recurrences of previously identified failures.
Queue benchmark source
CPU / FP32 MATRIX MULTIPLICATION
CUDA / KERNEL THROUGHPUT
8.46×
97.93 → 11.58 ms · 1024 × 1024 matrices
32 columns
inner-loop blocks
15 threads
OpenMP configuration
Profile
Reorder
Validate
Apple M5 Pro · macOS Release · 10-run median · original strided FP32 implementation as baseline.
CUDA / KERNEL THROUGHPUT
1.39B keys/s
500M uint32 keys · four-pass radix sort · 360 ms aggregate kernel time · RTX 3080 Ti Laptop GPU. Historical GPU-kernel measurement; allocations and transfers measured separately from the kernel scope.
Network I/O · Tail Latency
DIMS — Distributed C++ Messaging
A C++17 microservice messaging platform built around persistent Boost.Asio TCP connections, gRPC inter-service communication and a custom TLV binary protocol with compile-time type constraints. The TCP connection layer includes dedicated throughput and tail-latency benchmarks.
Boost.Asio
gRPC
C++17
Redis
Docker
- Isolated TCP layer: 50,000 concurrent loopback connections and 42.8K request-response exchanges/s.
- Recorded p50 / p99 round-trip latency of 0.93 / 5.44 ms across 17.9M exchanges, with zero failed exchanges in the 50K-connection run.
- Custom SFINAE-constrained TLV serialization across Qt and Boost stacks.
- ASan and GDB regression harness for concurrency stress testing.
NETWORK I/O / TAIL LATENCY
5.44ms
p99 round-trip time · loopback test
50K
loopback connections
42.8K
request-response exchanges / s
Isolated TCP connection layer · 50K loopback connections · 17.9M request-response exchanges · round-trip latency and completed-exchange throughput.
Bare-Metal Systems
ARMv8-A Kernel
Bare-metal bring-up on Cortex-A72 (Raspberry Pi 4B): assembly boot, MMU configuration, interrupt subsystem and cooperative scheduling, debugged through JTAG, GDB and UART tracing.
ARMv8-A
C/C++
ARM Assembly
GDB/OpenOCD
- EL1→EL0 exception-level transition with full context save and restore.
- TTBR-based multi-level page tables for kernel, MMIO and user space.
- Timer/UART interrupt handling, MMIO setup and SVC trap handling.
- Cooperative context switching validated through single-step JTAG debugging.
ARMv8-A / EXECUTION LEVELS
EL1
EL0
Kernel → user-space transition
MMU
IRQ
Context
Cortex-A72 · Raspberry Pi 4B
Let's talk
Seeking graphics, GPU-compute and C++ performance/systems roles, including low-latency trading infrastructure. Open to opportunities in Shanghai and across the APAC region.